McMaster Low Latency Labs

Thesis

A deadline is a correctness condition.

We build and measure systems where a late answer is a wrong answer.

Fig. 2REQ, then ACK, with two cycles of slack before the deadline.

Try it

It sees the pole d ms late. Push d past 96 ms and it falls.

Fig. 3Cart-pole, live

Simulated

or tap the drawing

Loop latency d

Inside the deadline by 66 ms. Small tilts die out.

Fig. 4Pole angle θ, last 8 s

Model

Fig. 3A cart-pole under state feedback, read d ms late. Simulated

Model details

Plant: Cart 1.0 kg on a ±0.6 m track. Pole: 0.2 kg point mass on a 0.6 m massless rod.
Controller: u = 42.8θ + 9.8ω + 3.1x + 4.6v, clipped to ±20 N. LQR gains, rounded. It reads the state from a ring buffer, d steps back.
Physics: RK4, fixed 1 ms step. The controller runs every step (1 kHz). Test nudge: 0.5 rad/s every 4 s, alternating sides.
Deadline: 96 ms: the largest d at which a 1 µrad tilt still dies out, found by bisection on this simulation at build time. The linearised loop's delay margin, 97.1 ms, agrees to within a step.

Fig. 5The same handshake, ACK half a cycle late. Late, so wrong.